Appeal No. 95-1536
Application 07/746,176
The invention pertains to a non-volatile semiconductor memory device. Claim 1 is illustrative
and reads as follows:
1. A non-volatile semiconductor memory device comprising:
a semiconductive substrate;
parallel bit lines provided above said substrate;
memory cells connected to said bit lines, said memory cells comprising cell blocks each of
which has a series array of memory cell transistors connected at a first node thereof to a corresponding
bit line associated therewith and connected at a second node thereof to said substrate, each of said
memory cell transistors having a carrier storage layer and a control gate electrode; and
means for sequentially programming selected memory cell transistors in such a manner as to
write a logical data into a certain memory cell transistor which is presently selected from said memory
cell transistors by injecting carriers by tunneling into the carrier storage layer of said certain memory cell
transistor thereby to increase a threshold value thereof, and for sequentially erasing the selected
memory cell transistors in a manner as to erase the data stored in said certain memory cell transistor by
removing the carriers accumulated in said carrier storage layer thereby to decrease the threshold value
of said certain memory cell transistor.
The references relied upon by the examiner as evidence of obviousness are:
Momodomi et al. (Momodomi ‘812) 4,959,812 Sep. 25, 1990
Sumihiro 60-182162 Sep. 17, 1985
(Japan, Kokai)
Momodomi et al. (Momodomi ‘900) 0 322 900 July 05, 1989
(European Patent Application)
Adler, “Densely Arrayed EEPROM Having Low-Voltage Tunnel Write,”
I.B.M. Technical Disclosure Bulletin, Volume 27, No. 6, Nov. 1984, pp. 3302-3307.
Masuoka et al. (Masuoka), “New Ultra High Density EPROM and Flash
EEPROM with NAND Structure Cell,” International Electron Devices
Meeting Technical Digest, Dec. 6-9, 1987, pp. 552-555.
2
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