Appeal No. 95-1536
Application 07/746,176
1995, respectively.
Appellants’ Invention
The invention is a non-volatile semiconductor memory device, and method for accessing data in
a non-volatile semiconductor memory device. The embodiment of Figures 1-4 includes parallel bit lines
BL1-BL8 provided on a semiconductor substrate. Memory cells M11…M88 are connected to the bit
lines. The memory cells comprise cell blocks B1-B8, each of which has a series array of memory cell
transistors connected at a first node QS11-QS81 to a corresponding bit line associated therewith and
connected at a second node to the substrate Vs. Each of the memory cell transistors has a carrier
storage layer 28 and a control gate electrode 32.
The memory includes a means for sequentially programming selected memory cell transistors to
write data into a certain memory cell transistor by injection of carriers by tunneling into the carrier
storage layer, and for sequentially erasing the selected memory cell transistors to erase the data stored
in the certain memory cell transistor by removing the carriers accumulated in the charge storage layer.
A data erase operation involves applying a 20 volt pulse to a control gate line SG1. The
selection transistor QS11 is rendered conductive, and cell block B1 is electrically connected with the
corresponding bit line BL1. A potential of 20 volts is simultaneously applied to the bit line BL1 while
zero volts is applied to the word lines WL1-WL8 in the M1 period of the illustrated
4
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