Appeal No. 95-1536
Application 07/746,176
All of the claims require sequential erasing of data from memory cells. None of the prior art
references teaches sequential erasing. Rather, each of the references teaches simultaneous erasing of
cells and, with the exception of Momodomi ‘812, the examiner has not tried to explain why one of
ordinary skill in the art at the time the invention was made would have found it obvious to modify the
prior art to use sequential erase of data cells. In re Fritch, 972 F.2d 1260, 1266, 23 USPQ2d 1780,
1783-1784 (Fed. Cir. 1992).
Although Momodomi ‘812 also teaches that data can be erased one byte at a time, this does
not constitute the sequential erasure of data from individual memory cells. In discussing Momodomi
‘812 at page 11 of his answer, the examiner takes the position that simultaneous erasure requires a
large power supply and that the sequential erasure of cells would have been obvious to permit the use
of a smaller power supply and that only those areas desired to be erased would be erased. This is not
persuasive. As noted by appellants, the examiner’s assertion to the effect that sequential erasure would
permit use of a smaller power supply is unsubstantiated. As further noted by appellants, the teachings
of the reference at column 11, lines 27-32, that no high gate voltage is needed for erasing data and that
the invention enables the reduction of the power dissipation in the EEPROM suggest that, contrary to
the examiner’s position, a large power supply is not needed in the prior art device.
The examiner takes the position that erasure of data in the prior art apparatus in only those cells
in which one might desire to erase data suggests sequential erasure of data. Even assuming the erasure
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