Appeal No. 1996-0347
Application No. 08/166,609
frequency is lowered when high operating speed is not needed
in order to conserve power. The frequency adjustment is based
on computer activity which is monitored by counting events
indicative of such activity. For example, the cache hit rate
may be monitored and the frequency of the system clock reduced
when the cache hit rate is above a predetermined level.
Representative independent claim 1 is reproduced as
follows:
1. An apparatus for use with a computer system for
reducing power consumption of the computer system, comprising:
a processor having a clocking input;
memory coupled to said processor;
means for producing a clocking signal having a frequency;
a counter coupled to said processor for counting a number
of events indicative of activity of the computer system during
a preset period of activity of said processor;
means coupled to said counter for periodically reading
the number of events counted by said counter;
means coupled to said periodic reading means and said
clocking signal producing means for adjusting the frequency of
the clocking signal based on the counted number of events; and
means coupled to said adjusting means for outputting the
frequency adjusted clocking signal to said processor clocking
input.
2
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