Appeal No. 1996-0347
Application No. 08/166,609
“based on the counted number of events.” Further, the
counting in Branson is for synchronization purposes (column
10, lines 12-14: “The counting sequence of the counter 38 and
the flip-flop 40 is synchronous with respect to the 5 MHZ
clock which is inverted by the NAND gate 50.”). Thus, the
frequency of the clock in Branson is not adjusted based on a
number of counted computer events, such as the number of times
a particular chip is accessed by the CPU. Branson also does
not count a number of main memory cycles as required by
instant claims 13 and 19.
Still further, even if Branson disclosed the counting of
a number of computer events, we remain unconvinced by any
reasoning of the examiner as to why the artisan would have
been led to use such a count as a basis for adjusting the
clock frequency in Intel.
Thus, we will not sustain the rejection of claims 1
through 6 and 13 through 18 under 35 U.S.C. 103 based on Intel
and Branson.
For the reasons supra, we also will not sustain the
rejection of claims 7 through 10 and 19 through 22 under 35
7
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