Appeal No. 96-0609
Application No. 08/024,803
The invention relates to a multiprocessor system which
allows the exchange of information between central memory and
processors via cache memory associated with each of these
processors. In particular, Appellants disclose on page 13 of
the specification that Figure 1 illustrates the multiprocessor
system having n processors CPU to CPU and a central random1 n
access memory RAM. The central memory is connected in
parallel to n shift registers, memory register RDM to RDM ,1 n
each having a memory size sufficient to store one block of
information. Each processor CPU includes a cache memory MCn j.
A shift register, processor register RDP , is connected by its
j
parallel port to each cache memory MC . Each memory register
j
RDM is connected by its serial port to the serial port of a
n
processor register RDP by a serial link LSj j.
The independent claim 1 is reproduced as follows:
1. A multiprocessor system comprising a
central memory (RAM) organized in blocks of
information (bi), a plurality of processors
(CPU . . . CPU . . . CPU ), a cache memory (MC )1 j n j
connected to each processor (CPU ) and organized
j
in blocks of information (bi) of the same size
as those of the central memory, a directory
(RG ) and a management processor (PG )j j
associated with each cache memory (MC ), means
j
for communicating addresses of blocks between
management processors (CPU ) and the central
j
memory (RAM), said multiprocessor system
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