Ex parte LITAIZE et al. - Page 9




          Appeal No. 96-0609                                                          
          Application No. 08/024,803                                                  


                    a set of memory shift registers (RDM  . . .                       
                                                        1                             
                    RDM  . . . RDM ), each of said memory shiftj          n                                                   
                    registers (RDM ) of said set having a size                        
                                  j                                                   
                    of one block of information and being                             
                    connected to the central memory (RAM) so as                       
                    to enable, in one memory cycle a parallel                         
                    transfer of a block of information (bi)                           
                    between said memory shift register and said                       
                    central memory, the memory shift registers                        
                    of said memory shift registers being                              
                    independent of each other for simultaneous                        
                    shifting of blocks of information, . . . a                        
                    set of serial links (LS  . . . LS  . . .1         j                                
                    LS ), each connecting a memory shift                              
                      n                                                               
                    register (RDM ) and a processor shift                             
                                 j                                                    
                    register (RDP ) for making a private                              
                                 j                                                    
                    connection between a paired memory shift                          
                    register and processor shift register                             
                    (RDM , RDP ) and transferring . . . blocksj    j                                                        
                    of information (bi) between the memory                            
                    shift register and the processor shift                            
                    register (RDM , RDP ) autonomously andj     j                                              
                    independently of other registers and other                        
                    serial links                                                      
          as recited in Appellants' claim 1.  The Examiner failed to                  
          show that the prior art suggested the desirability of the                   
          Examiner's proposed modification.  We are not inclined to                   
          dispense with proof by evidence when the proposition at issue               
          is not supported by a teaching in a prior art reference or                  
          shown to be common knowledge of unquestionable demonstration.               
          Our reviewing court requires this evidence in order to                      
          establish a prima facie case.  In re Knapp-Monarch Co., 296                 

                                          9                                           





Page:  Previous  1  2  3  4  5  6  7  8  9  10  11  12  13  14  Next 

Last modified: November 3, 2007