Appeal No. 96-0609
Application No. 08/024,803
processor shift register (RDP ) associated
j
with said cache memory (MC ), transferring
j
on a serial link (LS ) the contents of the
j
processor shift register (RDP ) to a memory
j
shift register (RDM ) of the same capacity,
j
associated with said processor in a set of
shift registers (RDM . . . RDM . . . RDM )1 j n
connected to the central memory (RAM).
On page 2 of the answer, the Examiner argues that Moran
teaches transferring a block from the central memory to one of
a set of memory shift registers (1007-1010) connected to
central memory. On page 6 of the answer, the Examiner argues
that the claim language reads on Moran's system in that there
is a plurality of shift registers 1007-1012 with one out of
the set being utilized for transmission of information.
As we pointed out above, Moran teaches in column 16
transferring a block of data from central memory (MM) to the
memory shift registers 1008-1010. Moran also teaches in
column 15 that the other memory shift registers do not store
blocks of data for transfer but store control data and
addresses that cause the transfer to occur. However, Moran
does not teach a set of shift registers in which each shift
register stores a block of data between the central memory and
11
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