Appeal No. 96-0862
Application 08/055,971
micro-code vector address selection means connected to
said micro-code means for selecting micro-code vectors to be
output from said output means without retrieving stored
addresses in said branch condition micro-vectors, said micro-
code vector address selection means comprising a pointer for
identifying said micro-vectors to be output and a plus one
adder for incrementing addresses stored in said pointer on
each clock cycle such that micro-code vector address selection
means selects next sequentially stored micro-code vectors in
said micro-code means after selecting branch condition micro-
vectors; and
data path logic unit coupled to said output means for
executing said micro-code vectors, wherein said data path
logic unit executes said branch condition vectors a clock
cycle after which said branch condition micro-code vectors are
retrieved from said micro-code means.
The examiner relies on the following references:
Joyce et al. (Joyce) 4,087,857 May 2, 1978
Keller et al. (Keller) 5,377,335 Dec. 27, 1994
Claims 1 through 6, 8 through 10, 12, 13, 15 through 17,
19 and 21 through 26 stand rejected under 35 U.S.C. 103 as
unpatentable over Keller. Claims 11 and 18 stand rejected
under 35 U.S.C. 103 as unpatentable over Keller in view of
Joyce.2
2It appears that the rejections of the claims under 35
U.S.C. 103 over Feil, U.S. Patent No. 5,058,007, and under 35
U.S.C. 102, as anticipated by Keller, have been withdrawn by
the examiner as they are not repeated in the latest answer.
Accordingly, these rejections are not before us on appeal.
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