Appeal No. 96-0862
Application 08/055,971
particular addressing technique for addressing instructions
“is generally an obvious engineering design choice” [second
supplemental answer, page 3].
With regard to the claimed data path logic unit, the
examiner contends [second supplemental answer, page 4] that
the ability to fetch and execute sequential instructions
in every clock cycle “is well-known and widely used in the
prior art’s processor.”
Thus, the examiner makes many allegations regarding what
is “well known” but provides no evidence of such. Further,
there is no clear explanation as to how such “well known”
elements and techniques are being applied to the specific
claim language before us.
Accordingly, in our view, the examiner has failed to
present a prima facie case of obviousness regarding the
instant claimed subject matter and we will not sustain the
rejection of claims 1 through 6, 8 through 13, 15 through 19
and 21 through 26 under 35 U.S.C. 103.
The examiner’s decision is reversed.
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