Appeal No. 96-1259
Application 08/201,185
pending claims in the application before us.
BACKGROUND
The subject matter on appeal is directed to a data
processing system that has a shared bus, and to controlling
transactions issued on the shared bus using coherency checks
(see specification, pages 1 and 2). Appellants admit in the
specification that shared buses are conventional (see
specification, page 3), and that coherency checking schemes
are known in the prior art (see specification, page 2).
Appellants recognized that a known problem in the prior art
was that coherency checking can be slow due to complex
handshaking requirements and multiple transactions such as
busy/abort signals (see specification, pages 3 to 5).
Appellants’ have attempted to overcome these drawbacks with
the prior art by providing a transaction queue in each client
module connected to the bus, and a bus controller, separate
from the client modules, which limits transactions on the bus
when a queue in one of the modules has less than a certain
amount of free space (see specification, page 5).
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