Appeal No. 96-1259
Application 08/201,185
main memory, instruction queue, and coherent transaction
buffer, we cannot sustain the rejection of claim 4 on appeal.
For the reasons which follow, we will sustain the decision of
the examiner rejecting claims 1 to 3 under 35 U.S.C. § 103,
and we will reverse the decision of the examiner rejecting
claim 4 under 35 U.S.C. § 103.
Rejection of Claims 1 to 3 Under 35 U.S.C. § 103:
Turning first to the rejection of claims 1 to 3 under §
103, we find that claims 1 to 3 on appeal would have been
obvious to one of ordinary skill in the art at the time the
invention was made in light of the teachings of Sindhu,
especially to the extent the invention is broadly set forth in
representative claim 1.
We find that Sindhu would have fairly taught or suggested all
of appellants’ broadly recited features of claim 1 of a data
processing system (Figure 1) having a bus (global bus 26), a
plurality of modules (14a, 14b, 14i), a bus controller
(arbiter 36 and/or controller 25), and means for determining
the amount of module queue free space which is "separate from
said modules" (arbiter 36 and/or controller 25; column 9,
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