Appeal No. 96-1259
Application 08/201,185
buffers) is not
discussed or suggested by Sindhu. We agree. The main memory
instruction queue and determining means coherent transaction
buffer operate in concert together to achieve an important
aspect of appellants’ invention of providing a system that
handles multiple transactions without imposing unnecessary
delays or design complexity. We find that the applied prior
art fails to teach or suggest such a main memory having an
instruction queue and a determining means having a coherent
transaction buffer. We find that the main memory of claim 4
is neither taught nor suggested by the applied reference to
Sindhu, and accordingly we cannot sustain the examiner’s
rejection under 35 U.S.C. § 103 as to claim 4.
In light of the foregoing, the differences between the
subject matter recited in claims 1 to 3 and the prior art are
such that the claimed subject matter as a whole would have
been obvious within the meaning of 35 U.S.C. § 103.
Accordingly, we shall sustain the standing rejections of
claims 1 to 3. We reach the opposite conclusion with respect
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