Appeal No. 96-2091
Application No. 08/230,544
be "asynchronous." The examiner contends that the SET signal
of Wong, derived from the CLOCK IN signal, is "asynchronous"
with the RESET signal, derived from a delayed version of the
CLOCK IN signal, since the SET and RESET signals are "not
aligned in phase" [supplemental answer, page 2]. The examiner
also contends that since the TEST and CLOCK IN signals are
"asynchronous" and are used to generate the first and second
signals, the first and second signals must also be
"asynchronous."
Appellant has defined "asynchronous" as "having no
predetermined or fixed time relationship to one another"
[specification, top of page 3]. In Wong, since the SET and
RESET signals are both derived from the CLOCK IN signal, the
SET and RESET signals cannot be "asynchronous," as that term
is employed in the instant claims. With regard to the
examiner's CLOCK IN/TEST signal explanation, these signals are
applied alternatively. If there is a TEST signal (HIGH) and
no CLOCK IN
signal (LOW), then the TEST signal passes through gate 14 as
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