Ex parte KOYANAGI et al. - Page 4




          Appeal No. 96-2696                                                          
          Application 08/167,415                                                      


               where LSB is set to logic 1 and the other bits are set to              
               logic 0.  Moreover, the attribute code is set to one byte              
               where the code indicating the data concerning the slice                
               data such as the attribute of [the] corresponding slice                
               is arranged.  Therefore, the slice start code is formed                
               by the data of 4 bytes in total (32 bits).                             
                    This slice start code is added in a unit of [a]                   
               slice without relation to [a] shortage of the data to be               
               transmitted.                                                           
                    The invalid code is added in such a manner that the               
               data where all the bits are set to logic 0 is added                    
               before the slice start code as required in unit[s]                     
               of the byte (8 bits).  This code is added in units                     
               of [a] slice only when there is a shortage of data                     
               to be transmitted.                                                     
                    Fig. 4 illustrates an invalid code to be added to a               
               c block [identified in the figure as a macro block].                   
               Namely, in this case, [a] total of 11 bits where [the]                 
               upper 7 bits are set to logic 0 and [the] lower 4 bits to              
               logic 1 are considered as a unit of the invalid code and               
               this invalid code is added before a valid code of the                  
               macroblock as many as the predetermined number of units.               
               [Spec. at 13-14.]                                                      
               Where invalid code is added to the data of a macroblock                
          in the manner shown in Fig. 4, the transmission data control                
          circuit 111 of Figure 1 can take the form shown in Figure 5                 
          (Spec. at 14, lines 19-22).  In figure 5, MUX (multiplexer)                 
          122, which is controlled by a controller 124, receives the                  
          output of macro block invalid code generating circuit 123 and               
          the output of N/M converter 121, which receives data from                   
          transmitting or send buffer 7 (Spec. at 14, line 22 to p. 15,               
          line 6).  Thus, the multiplexer combines data from the N/M                  
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