Ex parte KOYANAGI et al. - Page 5




          Appeal No. 96-2696                                                          
          Application 08/167,415                                                      


          converter with invalid code generated by macro block invalid                
          code generating circuit 123 (Spec. at 15, lines 2-6).  The                  
          controller 124                                                              
               controls the multiplexer 122 corresponding to the send                 
               buffer information and selects, when the send buffer 7                 
               does not generate [an] underflow condition, an output of               
               the N/M converter 121 or selects an invalid code                       
               outputted from the macroblock invalid code generating                  
               circuit 123 when the send buffer 7 is supposed to                      
               generate [an] underflow condition.  Therefore, the data                
               outputted from the multiplexer 122 mixes invalid codes of              
               the desired number of units. [Spec. at 15, lines 12-20).               
          Thus, an underflow condition sensed in send buffer 7 is                     
          corrected by inserting invalid codes into the output data                   
          stream provided by the send buffer.                                         
               Figures 6(A) and 6(B) show a prior art decoding apparatus              
          for decoding the data generated by the encoding apparatus of                
          Figures 1(A)-(C) (Spec. at 15, lines 21-24).  The received                  
          encoded data is temporarily stored in receiving buffer 32 and               
          then supplied to a variable length decoding circuit 33, the                 
          output of which is processed by inverse quantizing circuit 34               
          and then IDCT circuit 35 (Spec. at 15, last line to p. 16,                  
          line 22).  The variable length decoding circuit 33 removes any              
          invalid codes inserted by the encoding apparatus at the                     


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