Appeal No. 96-4032
Application 08/054,496
microprocessor (CPU) and the pulse generator (PG) have finished their instructions. Appellants further
state that the function of the sub-system 200 is to prevent a noise glitch on the master clock signal from
causing another operation to start before the one in process has finished.
On pages 9-11 of the specification, Appellants disclose the operation of sub-system 200 shown
in Figure 2. In particular, signals 204, 206 and 208 are generated by CPU and PG. The
CPURISEEN 204 signal is a signal from the CPU which is normally high except while the CPU is in the
process of performing an instruction which is started on the falling edge of MCLK 202 whereby the
signal is held low. The CPUFALLEN 206 signal is a signal from the CPU which is normally high
except while the CPU is in the process of performing an instruction which is started on the rising edge
of MCLK 202 whereby the signal is held low. The PGFALLEN 208 signal is a signal from the PG
which is normally high except while the PG is processing data which is started on the rising edge of
MCLK 202 whereby the signal is held low. The circuitry of Figure 2 delays the transition state of
MCLK 202 until CPURISEEN 204, CPUFALLEN 206 and PGFALLEN 208 signals have all
returned to the normally high state indicating that both the CPU and PG have finished and are ready to
start processing another instruction.
The independent claim 7 is reproduced as follows:
7. A clock circuit for providing a main clock signal having periodic logic state
transitions to an associated circuit which performs actions in response to said logic state transitions of
said main clock signal and provides completion signals indicating completion of said actions performed
in response to a preceding logic state transition of said main clock signal, wherein said clock circuit
3
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Last modified: November 3, 2007