Appeal No. 96-4032
Application 08/054,496
invention by the express teachings or suggestions found in the prior art, or by implications contained in
such teachings or suggestions. In re Sernaker, 702 F.2d 989, 995, 217 USPQ 1, 6 (Fed. Cir. 1983).
"Additionally, when determining obviousness, the claimed invention should be considered as a whole;
there is no legally recognizable 'heart' of the invention." Para-Ordnance Mfg. v. SGS Importers
Int’l, Inc., 73 F.3d 1085, 1087, 37 USPQ2d 1237, 1239 (Fed. Cir. 1995), cert. denied, 117 S.Ct.
80 (1996) citing W. L. Gore & Assocs., Inc. v. Garlock, Inc., 721 F.2d 1540, 1548, 220 USPQ
303, 309 (Fed. Cir. 1983), cert. denied, 469 U.S. 851 (1984).
Appellants argue on pages 5 and 6 of the brief that Sawtell and Essig, together or individually,
fail to teach or suggest feedback from the external circuit to control the duty cycle of the main clock
signal based on completion of a task triggered in response to a logic transition of the output clock
signal. Appellants further argue that both references lack a teaching or a suggestion of employing a
completion signal from an associated circuit indicative of completion of an action performed in response
to a previous logic state transition to control the duty cycle of the clock circuit.
We note that Appellants' claim 7 recites:
a main clock output means for providing said main clock signal to said associated
circuit; a clock signal input means for receiving an input clock signal having periodic
logic state transitions; completion signal input means for receiving said completion
signals from said associated circuit; means responsive to occurrence of a logic state
transition of said input clock signal for causing a logic state transition of said main clock
signal, said responsive means further comprising logic means responsive to receipt of a
said completion signal indicating completion of actions performed in response to a
preceding logic state transition of said main clock signal, for delaying said transition of
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