Appeal No. 96-4032
Application 08/054,496
comprises:
a main clock output means for providing said main clock signal to said associated circuit;
a clock signal input means for receiving an input clock signal having periodic logic state
transitions;
completion signal input means for receiving said completion signals from said associated circuit;
means responsive to occurrence of a logic state transition of said input clock signal for causing a
logic state transition of said main clock signal, said responsive means further comprising logic means
responsive to receipt of a said completion signal indicating completion of actions performed in response
to a preceding logic state transition of said main clock signal, for delaying said transition of said logic
state of said main clock signal until receipt of said completion signal.
The Examiner relies on the following references:
Essig et al. (Essig) 4,745,629 May 17, 1988
Sawtell 5,227,672 July 13, 1993
(filed Mar. 31, 1992)
Claims 7 through 14 stand rejected under 35 U.S.C.§ 103 as being unpatentable over Sawtell
in view of Essig.
Rather than reiterate the arguments of Appellants and the Examiner, reference is made to the
brief and answer for the respective details thereof.
OPINION
We will not sustain the rejection of claims 7 through 14 under 35 U.S.C. § 103.
The Examiner has failed to set forth a prima facie case of obviousness. It is the burden of the
Examiner to establish why one having ordinary skill in the art would have been led to the claimed
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