Appeal No. 96-4032
Application 08/054,496
turned off, but resumes operation of the timer from where it stopped when the refrigeration circuit is
turned on.
We agree that Essig teaches delaying a transition state of the off/on signal 21, but Essig does
not teach completion signals for the associated circuit, defrost element 22, or upon occurrence of a
logic state transition of an input clock, delaying an output clock signal state transition until receipt of the
completion signals. Thus, Essig does not teach means responsive to occurrence of a logic state
transition of the input clock signal for delaying the transition of a logic state transition of the output clock
signal until receipt of the completion signal from the associated circuit means responsive to occurrence
of a logic state transition of the input clock signal for delaying the transition of a logic state transition of
the output clock signal until receipt of the completion signal from the associated circuit as recited in
Appellants' claims.
Furthermore, we fail to find any suggestion of modifying Sawtell and Essig to provide a clock
circuit as recited in Appellants' claims. The Federal Circuit states that "[t]he mere fact that the prior art
may be modified in the manner suggested by the Examiner does not make the modification obvious
unless the prior art suggested the desirability of the modification." In re Fritch, 972 F.2d 1260, 1266
n.14, 23 USPQ2d 1780, 1783-84 n.14 (Fed. Cir. 1992), citing In re Gordon, 733 F.2d 900, 902,
221 USPQ 1125, 1127 (Fed. Cir. 1984). "Obviousness may not be
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