Appeal No. 96-4032
Application 08/054,496
said logic state of said main clock signal until receipt of said completion signal.
We note that the other independent claims recite similar limitations.
Upon a careful review of Sawtell and Essig, we find that neither reference teaches the above
limitations as recited in Appellants’ claims. In particular, neither reference teaches means responsive to
occurrence of a logic state transition of the input clock signal for delaying the transition of a logic state
transition of the output clock signal until receipt of the completion signal from the associated circuit.
Sawtell teaches in Figure 2 change over apparatus 320 for selection of either external clock #1
or external clock #2 which is supplied to device 308. Sawtell does not teach that device 308 provides
completion signals indicative of completion of actions performed by the device.
Essig teaches in Figure 1 a duty cycle timer 20 for a defrost heating element 22 of an associated
refrigerator circuit. The duty cycle time generator 20 includes two counters 30 and 32 which provide a
signal to control the relay 23 in which the relay remains off for an interval of 50 minutes and on for an
interval of 30 minutes. See column 4, lines 8-21. Thus, the two counters provide a series of square
waves of a duration of 10 minutes separated by an interval of 30 minutes. Essig also teaches that the
duty cycle timer 20 includes a hold circuit 36 that disables the duty cycle timer when the thermostat 35
signifies the operation of the refrigeration circuit has terminated its cooling operation. See column 4,
lines 40-53. Essig teaches that the hold circuit 36 is operative to suspend operation of the duty cycle
timer when the refrigeration circuit is
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