Ex parte SHOR et al. - Page 2




          Appeal No. 96-4052                                                          
          Application 08/198,511                                                      

               This is a decision on appeal under 35 U.S.C. § 134 from                
          the final rejection of claims 31, 33-46, 48, and 49.                        
               We affirm-in-part.                                                     
                                     BACKGROUND                                       
               The disclosed invention is directed to a method for                    
          photoelectrochemically etching silicon carbide (SiC), and                   
          particularly, to an etching method using selective etching of               
          different conductivity types of SiC.                                        
               Claim 31 is reproduced below.                                          
                    31.  A method for fabricating a semiconductor by                  
               selectively etching, said method comprising the steps of:              
                    providing a substrate;                                            
                    forming a first semiconducting layer on said                      
               substrate, said first semiconducting layer comprising                  
               p-type silicon carbide, and requiring a first voltage for              
               charge transport at a surface of said layer in a given                 
               electolytic etching solution;                                          
                    forming a second semiconductor layer on said first                
               layer, said second layer comprising n-type silicon                     
               carbide, and requiring a second voltage for charge                     
               transport at a surface of said second layer in said given              
               electrolytic etching solution which is lower than said                 
               first voltage;                                                         
                    placing said substrate into said given electrolytic               
               etching solution;                                                      
                    applying a bias voltage to said second semiconductor              
               layer which is between said first and second voltages;                 
               and                                                                    
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