Appeal No. 97-1205 Page 2
Application No. 08/357,551
CPU, whereas codes accessed from a low-speed memory are
fetched
to the instruction queue buffer and then to the CPU one cycle
later. Claim 5 is illustrative of the claimed invention, and
it reads as follows:
5. In a microcomputer, a method for a central processing
unit (CPU) to fetch an instruction code from a memory
when an instruction queue buffer does not contain the
instruction code, comprising the steps of:
fetching the instruction code from a high-speed
memory directly to the CPU, if the instruction
code is in said high speed memory;
fetching the instruction code from a low-speed
memory to the instruction queue buffer, if said
instruction code is in said low-speed memory;
waiting until said instruction code is fetched
from said low-speed memory into said instruction
queue buffer; and
fetching the instruction code from the
instruction queue buffer to the CPU, one cycle
after the instruction code has been fetched from
said low-speed memory to the instruction queue
buffer.
The prior art reference of record relied upon by the
examiner in rejecting the appealed claim is:
Matsuo et al. (Matsuo) 4,796,175 Jan. 03,
1989
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