Appeal No. 97-1205 Page 4
Application No. 08/357,551
the instruction code from a low-speed memory (i.e. main
memory) to the instruction queue buffer if the instruction
code is in the low-speed memory.” The examiner refers to the
abstract, and column 1, line 10-column 4, line 47, or rather
the entire patent, to support his assertion. Appellants, on
the other hand, argue (Brief, pages 7-9) that
instruction codes from the cache memory (high-speed memory)
are placed in the instruction queue buffer before going to the
CPU. We do not find the teachings of Matsuo to support the
examiner’s statements and, therefore, agree with appellants.
Matsuo disclose in column 2, lines 55-59, “when an amount
of instruction data stored in the instruction queue 1
decreases to an amount below a constant value, ... the
instruction queue 1 searches the instruction cache 4.” In
column 3, lines 11-16, Matsuo teach that when “the cache was
hit, the instruction queue 1 queues the instruction data
stored in the instruction cache 4. Therefore, there is no
need to wait until the instruction is fetched from the main
memory and the possibility such that the instruction queue
becomes empty can be reduced.” In other words, instructions
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