Appeal No. 97-1205 Page 5
Application No. 08/357,551
from the high-speed memory (the instruction cache 4) are
fetched to the instruction queue 1, so that the queue does not
become empty, and therefore are not fetched directly to the
CPU, as recited in claim 5. Furthermore, as pointed out by
appellants (Brief, page 7), Figure 1 of Matsuo shows the
instruction cache feeding directly into the instruction queue
only. Accordingly, all data fetched from the instruction
cache 4 must go to the instruction queue 1, and not directly
to the CPU.
Regarding the recitation of waiting one cycle between
fetching instruction codes from the slow-speed memory to the
instruction queue buffer and fetching the codes from the
instruction queue buffer to the CPU, the examiner admits that
Matsuo does not explicitly disclose any delay (Answer, page
4). Although the examiner attempts to explain why it would
have been obvious to one of ordinary skill in the art at the
time of the invention, he fails to provide any evidence to
support his rationale.
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