Appeal No. 97-1205 Page 3
Application No. 08/357,551
Claim 5 stands rejected under 35 U.S.C. § 103 as being
unpatentable over Matsuo.
Reference is made to the examiner's answer (Paper No. 25,
mailed June 24, 2996) for the examiner's complete reasoning in
support of the rejections, and to the appellants’ briefs
(Paper Nos. 22 and 24, filed March 1, 1996 and April 1, 1996,
respectively) and reply brief (Paper No. 27, filed August 26,
1996) for the appellants’ arguments thereagainst.
OPINION
We have carefully considered the positions of the
examiner and the appellants and we will reverse the
obviousness rejection of claim 5.
Claim 5 requires an instruction code fetched from a high-
speed memory to go “directly to the CPU”, whereas an
instruction code fetched from a low-speed memory goes first
into the instruction queue buffer and then to the CPU. The
examiner is of the opinion (Answer page 6) that Matsuo
“explicitly disclose fetching the instruction code from a
high-speed memory (i.e. cache memory) directly to the CPU if
the instruction code is in the high-speed memory, and fetching
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