Ex parte HARDEE - Page 7




          Appeal No. 1997-2294                                       Page 7           
          Application No. 08/284,183                                                  


               The examiner errs in determining the content of the prior              
          art.  Although he refers to McClure’s memory cells 30, the                  
          memory cells 30 are part of a column in a sub-array 12  of an               
                                                                n                     
          IC                                                                          
          memory 1.  Col. 8, ll. 10-13 (referring to Fig. 4).  Figure 2               
          of the reference shows that McClure’s sense/write circuits 13,              
          i.e., the reference’s sense amplifiers (SA0-SA7), are separate              
          from the sub-array 12 .  Because McClure’s memory cells 30 are              
                               n                                                      
          not part of the reference’s sense amplifiers 13, the examiner               
          fails to show a teaching of the claimed “sense amplifier                    
          arrangement for an integrated circuit memory comprising: a                  
          latch circuit ....”  The absence of this showing negates                    
          anticipation.  Therefore, we reverse the rejection of claims                
          8, 9, 14-21, 29, 30, 32, 33, and 50 under 35 U.S.C. § 102(e).               
          Next, we address the novelty of claims 22-28.                               


                               Novelty of Claims 22-28                                
               Regarding claims 22-28, the examiner makes the following               
          assertion.                                                                  
               McClure shows all the limitations of the claimed                       
               sense amplifier arrangement in Figs. 1-10                              
               (especially figs. 4-5), comprising a latch circuit                     







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