Appeal No. 1997-2294 Page 11
Application No. 08/284,183
22-28 under 35 U.S.C. § 102(e). Next and last, we address the
novelty of claims 40-49.
Novelty of Claims 40-49
Regarding claims 40-49, the examiner makes the following
assertion:
McClure shows ... at least one pair of bit lines SN-
SN- of the memory; a local data write driver circuit
WRSEL, 38j, 54T-57T, 59T-60T, 53, 54C-57C, and 59C-
60C coupled to the latch circuit 48, the driver
circuit including a plurality of transistors coupled
together; the local data write driver circuit being
respectively coupled to a data write control signal
38j and WRSEL so that a power supply voltage (Vcc
inside 48) may be (note that "may be" is a broad
term so that the Examiner can interpret it as "may
be not") selectively coupled via the local data
write driver circuit to an internal node of the
latch circuit 48 and thus to a corresponding bit
line SN-SN-, in accordance with the data write
control signal 38j and WRSEL (note that the power
supply voltage VCC inside 48 may not be selectively
coupled to the latch circuit because of an isolation
signal ISO to pass transistors 43). (Examiner’s
Answer at 5-6.)
The appellant replies, “circuit 48 of McClure does not have a
power supply voltage selectively coupled via a local data
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