Appeal No. 1997-2294 Page 13
Application No. 08/284,183
The examiner fails to show a teaching of this limitation
in the prior art. Although he refers to McClure’s sense nodes
SN and SN_, the sense nodes are “complementary lines on the
opposite side of pass transistors 43 from input/output lines
21 and 21 ....” Col. 9, ll. 45-46. “[E]ach of passj j-
transistors 43 ha[s] its gate controlled by an isolate signal
ISO.” Id. at ll. 40-41. “ISO will be driven to a high logic
level during
write operations to turn off pass gates 43, so that data
written by the write side of sense/write circuits 13 will not
be sensed by sense amplifiers 48 and output onto output bus 20
during such operations.” Col. 14, l. 68 - col. 15, l. 5.
Because pass transistors 43 are turned off during write
operations, lines SN and SN_ are not driven during write
operations. Accordingly, the examiner fails to show a
teaching of the claimed “power supply voltage [that] may be
selectively coupled via said local data write driver circuit
to an internal node of said latch circuit and thus to a
corresponding bit line, in accordance with said data write
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