Appeal No. 97-2630
Application 08/186,050
1. An apparatus comprising a SCSI controller and an
Ethernet controller integrated onto a single
integrated circuit chip, wherein the SCSI and
Ethernet controller include digital control
circuitry coupled to buffers, and the Ethernet
controller includes analog circuitry, wherein
circuitry on the integrated circuit chip is
configured to limit noise generated in the analog
circuitry by signals in the digital control
circuitry.
15. An integrated circuit comprising:
internal circuitry;
buffers; and
V leads including a first set of V leadsss ss
connected to the internal circuitry and a second set
of V leads connected only to the buffers.
ss
Opinion
We sustain the rejection of claim 1. Our affirmance of
the obviousness rejection is based only on the arguments
presented by appellants in their brief. Arguments not raised
in the brief are not before us, are not at issue, and thus are
considered as waived.
The rejection of claims 13 and 15 cannot be sustained. A
reversal of the rejection on appeal should not be construed as
an affirmative indication that the appellants’ claims are
patentable over prior art. We address only the positions and
4
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