Appeal No. 97-2630
Application 08/186,050
were well known to one with ordinary skill in the art and
would have been readily applied by one with ordinary skill in
the art when integrating analog and digital circuits together.
For support, the examiner cited to Partovi, Sundby, Roger,
Fujita, and Kimura (Examiner’s Answer at pages 5-6). We agree
with the examiner that a standard digital noise reduction
technique for integrated circuit chips or a digital noise
reduction technique that would have been well known to one
with ordinary skill in the art would be sufficient to meet the
claimed feature “to limit noise generated in the analog
circuitry by signals in the digital control circuitry.”
On pages 5-6 of the appeal brief, the appellant argues:
For a person of ordinary skill in the art to
integrate SCSI and Ethernet controllers on a chip,
the person would need to realize that circuitry
should be configured to isolate analog and digital
components as well as to reduce the effect of a 48
milliamp input signal as done by separating V lines
ss
for buffers (Appellant’s specification page 9, line
19 through page 11, line 10) and configuring buffers
to switch current in delayed steps (Appellant’s
specification page 11, line 11 through page 18, line
4), and by isolating the power supplies (Appellant’s
specification page 22, line 11 through page 25, line
23).
As we have already noted above, the arguments of the appellant
are not commensurate in scope with what has been recited in
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