Appeal No. 97-2630
Application 08/186,050
rationale as set forth by the examiner and on which the
examiner’s rejection of the claims on appeal is based.
As per claim 1, the appellant states (Brief at page 2):
Appellant’s invention is an integration of
components of a SCSI controller and an Ethernet
controller onto a single chip with circuitry
configured to reduce noise generated by digital
signals so that the analog circuitry will operate
within an acceptable error margin. High current in
the digital SCSI controller circuitry has previously
prevented manufacturers from integrating SCSI and
Ethernet controllers due to an unacceptable errors
created in the analog Ethernet components. (Page 2,
lines 16-34).
The appellant’s specification explains that with the presence
of sensitive analog components in the Ethernet controller,
such as the phase lock loop, noise generated from digital
signals from SCSI components has prevented manufacturers from
integrating SCSI and Ethernet components together. See
specification at page 2.
Duschatko does not disclose integrating an SCSI
controller and an Ethernet controller together on a single
integrated circuit chip as is required by claim 1. The
appellant acknowledges that combining analog and digital
circuits onto one integrated circuit chip is generally within
the knowledge of one with ordinary skill in the art, as is
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