Appeal No. 1997-1197
Application 08/130,255
read signal which can generate read addresses for the two
different sequences. Appellants do not point out what
structure is relied on in figures 10a and 10b. While it would
be easy to say that the whole circuit shown in one of figures
10a or 10b is the corresponding structure because Appellants
fail to identify any specific structure, we look at the
disclosed structure. It appears that the only structure
needed to perform the function is a read/write address logic
block, e.g., element 1008. Kajihara discloses a read address
generator 52 and write address generator 53 (figure 1) to read
and write to the page memory 51 in the sequences shown in
figures 2A-2D. The description of figure 3 does not show the
structure to read and write to the page memory to perform the
operations summarized in figure 5, but read and write address
generator structure similar to that of figure 1 must exist to
scan the page memory as described for the output raster scan
mode. We find that the address logic to read and write to the
buffer memory in Kajihara is the same as or an equivalent of
the structure described because Appellants disclose no more
detail of the structure to perform the claimed functions than
what is shown in Kajihara.
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