Appeal No. 1997-1695
Application No. 08/496,121
Claim 1 is illustrative of the invention and reads as
follows:
1. A boosted potential generating circuit comprising:
a P-channel MOS transistor connected between a
first node and a boosted potential node for
outputting a boosted potential, said P-channel
MOS transistor having a gate electrode connected
to a second node;
first potential means for supplying a first
signal having a first level of a positive
precharge potential and a second level of a
potential higher than the precharge potential to
said first node; and
second potential means for supplying a second
signal having a phase opposite to said first
signal supplied by said first potential means
and having a third level of the positive
precharge potential and a fourth level of a
potential higher than the precharge potential to
said second node.
The Examiner’s Answer cites the following prior art
references:1
The Examiner explicitly relies only on Ichimura as the basis for the1
prior art rejections. The Yilmaz, Truong, and Koford references are cited as
3
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