Appeal No. 1997-1695
Application No. 08/496,121
claim 20. We note, however, that each of independent claims
12 and 20 include the requirement that the applied signals to
the drive transistor be opposite in phase, a feature which we
found lacking in Ichimura as discussed supra. Accordingly,
because the Examiner has not established a prima facie case of
obviousness since all of the limitations of the claims are not
taught or suggested by the prior art, the 35 U.S.C. § 103
rejection of independent claims 12 and 20 as well as dependent
claims 2 through 6, 8, 14 through 16, 19, 21, 22, and 25
through 27 is not sustained.
Finally, we have reviewed the Truong, Yilmaz, and Koford
references cited in the Answer as evidentiary support for the
Examiner’s assertion of the well known aspects of buffer
generated clock signals (Truong) and single chip architecture
(Yilmaz and Koford). We find no disclosure in any of the
references which would overcome the innate deficiencies of
Ichimura in disclosing the application of input signals to a
drive transistor which are opposite in phase.
In summary, we have not sustained either of the
Examiner’s rejections of the claims on appeal. Accordingly,
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