Appeal No. 1997-1695
Application No. 08/496,121
Accordingly, we reverse.
We consider first the rejection of claims 1 and 10 under
35 U.S.C. § 102(b) as being anticipated by Ichimura.
Anticipation is established only when a single prior art
reference discloses, expressly or under the principles of
inherency, each and every element of a claimed invention as
well as disclosing structure which is capable of performing
the recited functional limitations. RCA Corp. v. Applied
Digital Data Systems, Inc., 730 F.2d 1440, 1444, 221 USPQ 385,
388 (Fed. Cir.); cert. dismissed, 468 U.S. 1228 (1984); W.L.
Gore and Associates, Inc. v. Garlock, Inc., 721 F.2d 1540,
1554, 220 USPQ 303, 313 (Fed. Cir. 1983), cert. denied, 469
U.S. 851 (1984).
With respect to independent claim 1, the Examiner
attempts to read the claimed limitations on the booster
circuit illustrated in Figure 1 of Ichimura. In the
Examiner’s view (Answer, page 4), the transistor QB on the far
right of
Ichimura’s Figure 1 corresponds to the claimed PMOS drive
transistor and the unillustrated potential means which supply
the
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