Appeal No. 1997-2383
Application No. 08/150,782
ground voltage in response to an address transition detection
signal.
Claim 5 is illustrative of the claimed invention, and it
reads as follows:
5. A dynamic random access memory comprising:
an array of rows and columns of memory cells;
parallel word lines associated with the rows of said
memory cells;
parallel bit lines transverse to said word lines and
associated with the columns of said memory cells;
a sense amplifier coupled to said array of memory
cells to read out data directly from said memory cells;
row decoder means, coupled to said word lines, for
receiving a row address signal, and for selecting a
corresponding one of said word lines;
column decoder means, coupled to said bit lines and
said sense amplifier, for receiving a column address
signal to select a corresponding one of said bit lines;
first data lines coupled to said bit lines by
transfer gates which are selectively controlled by said
column decoder means whereby readout data output from
said sense amplifier is transferred to said first data
lines;
a data input/output buffer coupled to said first
data lines and including a CMOS current mirror
differential amplifier activated in a ready mode to amplify
the readout
data on said first data lines;
2
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