Appeal No. 1997-2383 Application No. 08/150,782 equalizing the second data lines. The same holds true for Minato. Nakano discloses 1/2 Vcc in a DRAM, but such potential level is not reset as a result of an address transition detection signal as claimed. 7Page: Previous 1 2 3 4 5 6 7 8 9 NextLast modified: November 3, 2007