Appeal No. 1997-2383
Application No. 08/150,782
Appellants argue (Brief, page 5) that Shinoda does not
teach the “address transition detecting means,” the “precharge
potential level of the second data lines” or the particular
“equalization circuits” of the claimed invention. Appellants
also argue (Brief, page 6) that Hayakawa discloses a SRAM
which cannot use a 1/2 Vcc pre-charge scheme, and that
Hayakawa does not disclose an intermediate potential between
Vcc and ground for equalizing the second data lines, the I/O
output differential amplifier, or the “equalization means.”
With respect to Nakano, Appellants argue (Brief, page 8) that
Nakano discloses equalizing transistors in a DRAM, but “does
not teach the provision of CMOS differential amplifiers
arranged at the front stage of a latch circuit, with an
intermediate potential between a power source voltage and a
ground voltage of the memory being equalized on the claimed
'second data lines' at the input to the data latch circuit.”
Lastly, Appellants argue (Reply Brief, page 1) that the
combining of the references is based on hindsight speculation.
We agree. Hayakawa is completely silent concerning the use of
a DRAM, wherein the address transition means is arranged to
cause an intermediate potential between Vcc and ground for
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