Appeal No. 1997-2383
Application No. 08/150,782
second data lines connected to said first data lines
through said data input/output buffer and passing data
amplified by said differential amplifier thereof;
address transition detecting means for detecting
transition of the row and column address signals, and for
generating an address transition detection signal;
equalizing means, coupled to said second data lines
and said address transition detecting means, for
resetting said second data lines, to which the amplified
data from said differential amplifier is supplied, at a
preselected potential level, said equalizing means
including switching means for connecting said second data
lines to said preselected potential level in
response to the address transition detection signal, said
preselected potential
level being an intermediate potential between a power
source voltage and a ground voltage of said memory; and
data latch means connected to said differential
amplifier through said second data lines for
latching the amplified data.
The references relied on by the examiner are:1
1The following references are cited for their teachings of
an intermediate voltage (i.e., 1/2 Vcc):
Watanabe et al. (Watanabe) 4,967,395 Oct. 30,
1990
Tsuchida et al. (Tsuchida), “The Stabilized Reference-Line
(SRL) Technique for Scaled DRAM’s,” IEEE Journal of Solid-
State Circuits, Vol. 25, No. 1, pages 24-29 (Feb. 1990).
3
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