Appeal No. 1997-2383
Application No. 08/150,782
Reference is made to the briefs and the answer for the
respective positions of the appellants and the examiner.
OPINION
The obviousness rejection of claims 3-6 and 8-16 is
reversed.
According to the examiner (Answer, page 4), Shinoda
discloses (Figs. 1-2 and column 6, lines 23-46) all of the
means and steps of claims 3-6 and 8-16, except for a teaching
of the “address transition means” and the 1/2 Vcc precharge
potential level of the second data lines. The examiner
concludes (Answer, page 6) that it would have been obvious to
apply the teachings of Hayakawa or Minato to Shinoda to
improve the data read out operation because the secondary
references disclose high speed operation through the use of
address transition detection. The examiner is also of the
opinion (Answer, pages 6 and 7) that it would have been
obvious to the skilled artisan “to equalize the data bus lines
of Shinoda as taught by Nakano to an intermediate potential
level between Vcc and ground in order to reduce noise and
decrease the time it takes the sense amplifier to bring the
data bus lines to their full complementary logic levels.”
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