Appeal No. 1997-3161
Application No. 08/450,553
1993
(Effectively Filed Jul. 20,
1989)
Caywood 5,235,544 Aug. 10,
1993
(Filed Nov. 09, 1990)
Anantha et al. (Anantha), “Electrically Erasable Floating Gate
Field Effect Transistor Memory Cell,” 17 IBM Technical
Disclosure Bulletin, no. 8, 2311-13 (January 1975).
Dockerty, “Nonvolatile Memory Array with Single FAMOS Device
Per Cell,” 17 IBM Technical Disclosure Bulletin, no. 8, 2314-
15 (January 1975).
Kikuchi et al. (Kikuchi), “A 2048-Bit N-Channel Fully Decoded
Electrically Writable/Erasable Nonvolatile Read Only Memory,”
1st European Solid-State Circuits Conference (ESSIRC), Kent,
England, 66-7 (September 1975).
Claims 6-9, 43, 45, 46, and 51-57 stand finally rejected
under the “enabling” clause of the first paragraph of 35
U.S.C.
§ 112, as well as under the second paragraph of 35 U.S.C.
§ 112 for failure to particularly point out and distinctly
claim the invention. Claims 6-9, 43, 45, 46, and 51-57 stand
further finally rejected under 35 U.S.C. § 103 as being
unpatentable over Haddad in view of Anderson.
Rather than reiterate the arguments of Appellant
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