Appeal No. 1997-3442 Page 2
Application No. 08/210,288
The invention pertains to a non-volatile semiconductor
memory device, best described by reference to Figure 7A and to
independent claim 1 reproduced as follows:
1. A nonvolatile semiconductor memory device comprising:
a plurality of NAND memory cells each having first and
second terminals and constituted by connecting a plurality of
memory cells each having a control gate in series with each
other, said NAND memory cells including adjacent first and
second NAND memory cells;
bit lines commonly used for NAND memory sets each
constituted by at least said first and second NAND memory cells
of said NAND memory cells, said bit lines being coupled to the
first terminals of said NAND memory cells;
source lines commonly used for the NAND memory set each
constituted by at least said first and second NAND memory cells
of said NAND memory cells, said source lines being coupled to
the second terminals of said NAND memory cells;
first selection transistors arranged between the first
terminal of the first NAND memory cell and said bit line;
second selection transistors arranged between the first
terminal of said second NAND memory cell and said bit line;
third selection transistors arranged between the second
terminal of the first NAND memory cell and said source line;
fourth selection transistors arranged between the second
terminal of said second NAND memory cell and said source line;
a first control gate line coupled to at least control
gates of said first selection transistors;
a second control gate line coupled to at least control
gates of said second selection transistors;
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