Appeal No. 1997-3442 Page 5
Application No. 08/210,288
within word block WB0) as corresponding to the claimed first,
second, third and fourth selection transistors.
Appellants argue that the instant invention provides for
selection transistors which independently connect/disconnect
the first and second NAND memory cells to the bit/source lines
by gate lines SG1-SG4. Appellants provide a further argument
regarding a certain order of gate lines of the NAND memory
cells in Adler [principal brief, page 7]. Since independent
claim 1 is not concerned with any such “order” and the claim
recites nothing about the transistors independently connecting
or disconnecting the first and second NAND memory cells,
appellants’ arguments in these regards are not persuasive.
However, independent claim 1 is very clear on the specific
and various connections of the source and bit lines, first and
second terminals of the NAND memory cells and the selection
transistors, as well as the control gate lines. The examiner
has not clearly indicated how each of these recited connections
is met by Adler. For example, it is clear from the claim
language that the various recited selection transistors are
connected to different terminals of the NAND memory cells and
bit and source lines. As appellants point out in the reply
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