Appeal No. 1997-3442 Page 6
Application No. 08/210,288
brief, the examiner has indicated, on the marked-up copy of
Figure 1 of Adler, that the word blocks, or NAND memory cells
themselves, include the first to fourth selection transistors.
This is contrary to the claimed invention which clearly
indicates that these selection transistors are elements
separate from the NAND memory cells. Therefore, since the
transistors identified by the examiner in Adler as the claimed
selection transistors are not arranged in the same manner as
required by independent claim 1, i.e., between terminals of the
NAND memory cells and bit or source lines, Adler cannot be said
to anticipate the instant claimed invention.
Accordingly, the examiner’s rejection of claims 1, 3, 4
and 6 through 8 under 35 U.S.C. 102(b) will not be sustained.
With regard to the rejections of claims 2, 5 and 9 under
35 U.S.C. 103, we also will not sustain these rejections
because Choi and/or Kanazawa do not provide for nor suggest the
deficiencies noted supra with regard to Adler. Therefore, we
do not reach dependent claims 2, 5 and 9.
The examiner’s decision is reversed.
REVERSED
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