Appeal No. 1997-3730
Application No. 08/095,147
After careful review of the applied prior art in light of
the arguments of record, we are in agreement with Appellants’
position as stated in the Brief. We note that a relevant
portion of independent claim 1 recites:2
at least one diode formed within said inactive
region of said wafer in registry with said
retainer and near the outer periphery of said
wafer; ...
In addressing this limitation, the Examiner initially calls
attention to Lee which is directed to the prevention of arcing
in plasma etch systems. As correctly set forth by the
Examiner, Lee’s approach to this problem is to provide a
conductive path for electrical charges by inserting conductive
plugs through the protective surfaces surrounding the wafer on
the top surface of a metal pedestal. As motivation for
incorporating the conductive plugs within an inactive region
of a wafer as recited in the claims on appeal, the Examiner
turns to the CMOS integrated circuit disclosure of Harrington.
As asserted by the Examiner, the Figure 6 illustration and
accompanying description in Harrington disclose the
2Independent claim 7, which is directed to the same
embodiment of the invention, has a similar recitation.
7
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