Appeal No. 1997-3730
Application No. 08/095,147
providing an avenue for charge flow, erects a barrier to the
flow of charge through buried channel regions of a
semiconductor. In view of the above, we are left to speculate
why one of ordinary skill would have found it obvious to
modify the applied prior art to make the combination suggested
by the Examiner. The only reason we can discern is improper
hindsight reconstruction of Appellants’ claimed invention. In
order for us to sustain the Examiner’s rejection under 35
U.S.C. § 103, we would need to resort to speculation or
unfounded assumptions or rationales to supply deficiencies in
the factual basis of the rejection before us. In re Warner,
379 F.2d 1011, 1017, 154 USPQ 173, 178 (CCPA 1967), cert.
denied, 389 U.S. 1057 (1968), rehearing denied, 390 U.S. 1000
(1968).
We are further of the opinion that, as asserted by
Appellants, even assuming arguendo that proper motivation were
established for the Examiner’s proposed combination, the
resulting system would fall far short of meeting the specific
requirements of the claims on appeal. The appealed claims set
forth a specific positional relationship between the formed
diode, the inactive region of the wafer, and the wafer
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