Ex parte CHANG - Page 2




          Appeal No. 1998-0343                                                        
          Application 08/439,209                                                      


               The disclosed invention pertains to an arrangement of                  
          components to form a nonvolatile memory structure.                          
          Representative claim 4 is reproduced as follows:                            
               4.  A nonvolatile memory structure for storing a                       
          plurality of bits of data comprising:                                       
               a semiconductor substrate;                                             
               a first doped region and a second doped region, wherein                
          the first and second doped regions lie within the substrate                 
          and are spaced apart from each other;                                       
               a channel region lying within the substrate and between                
          the first and second doped regions;                                         
               a first gate dielectric layer overlying the substrate;                 
               a first floating gate and a second floating gate                       
          overlying the substrate, wherein the first and second floating              
          gates:                                                                      
               are spaced-apart from each other; and                                  
               each of the first and second floating gates does not                   
          extend across all of the channel region in any direction;                   
               an intergate dielectric layer overlying the first and                  
          second floating gates;                                                      
               a first conductive member and a second conductive member,              
          wherein:                                                                    
               the first conductive member lies adjacent to the first                 
          floating gate and overlies a first portion of the channel                   
          region that is not covered by the first or second floating                  
          gates;                                                                      


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