Appeal No. 1998-0343
Application 08/439,209
Appellant makes two primary arguments in support of his
position that Ma does not fully disclose the claimed
invention. First, appellant argues that Ma does not disclose
the recitation that “each of the first and second floating
gates does not extend across all of the channel region in any
direction.” Second, appellant argues that the examiner has
improperly considered an array of memory cell structures in Ma
rather than a single structure as claimed. The examiner
disagrees with both arguments.
With respect to appellant’s first argument, we agree with
the examiner. We note that the channel region in question can
be viewed as a three-dimensional volume bounded by the top
surface of the substrate and having length, width and depth
dimensions determined by the length, width and depth
dimensions of the source and drain regions of the transistors.
The depth dimension is clearly irrelevant here because the
floating gates of the invention and of Ma are situated above
the surface of the substrate. If one considers the space
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