Appeal No. 1998-0747
Application 08/609,958
Yajima discloses a microprocessor system. Referring to
Figure 1, assuming a second processor unit 12 fails, a second
processor connection circuit 23 sends a fault signal to the first
2
processor unit 11 via the processor interface line 14. The fault
signal is detected by the fault detector 43 in the first processor
1
unit, which prompts the first common memory controller 47 to
1
access the second control set saved in the common memory area 32
via the interface controllers 58 and 62 (Figure 6). The first
processor unit then processes the second control set to perform
the functions of the failed second processor unit.
Entenman discloses a system wherein operating modem modules
10 10 are physically separated from a redundant spare module 12
1- n
(Figure 1). The redundant module 12 is idle until a control
system detects a failure in one of the modules 10 and activates
the redundant module 12 to operate in its place.
Ozaki teaches a plurality of switches 30-1 and 30-2 in a
redundant system to route data from an active unit such as 111’
to a spare unit such as 121’ when a fault is detected in the
active unit.
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